138
9152BINDCO02/10
ATA8743
23. USI Universal Serial Interface
23.1 Features
" Two-wire Synchronous Data Transfer (Master or Slave)
" Three-wire Synchronous Data Transfer (Master or Slave)
" Data Received Interrupt
" Wake up from Idle Mode
" In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode
" Two-wire Start Condition Detector with Interrupt Capability
23.2 Overview
The Universal Serial Interface (USI), provides the basic hardware resources needed for serial
communication. Combined with a minimum of control software, the USI allows significantly
higher transfer rates and uses less code space than solutions based on software only. Interrupts
are included to minimize the processor load.
A simplified block diagram of the USI is shown in Figure 23-1 on page 138. For the actual place-
ment of I/O pins. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in
bold. The device-specific I/O Register and bit locations are listed in the Register Descriptions
on page 146.
Figure 23-1. Universal Serial Interface, Block Diagram
The 8-bit Shift Register is directly accessible via the data bus and contains the incoming and
outgoing data. The register has no buffering so the data must be read as quickly as possible to
ensure that no data is lost. The most significant bit is connected to one of two output pins
depending of the wire mode configuration. A transparent latch is inserted between the Serial
Register Output and output pin, which delays the change of data output to the opposite clock
edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin
independent of the configuration.
Two-wire Clock
Control Unit
DO
(Output only)
DI/SDA
(Input/Open Drain)
USCK/SCL
(Input/Open Drain)
4-bit Counter
USIDR
USISR
D Q
LE
USICR
CLOCK
HOLD
TIM0 COMP
[1]
3
0
1
2
3
0
1
2
0
1
2
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